1. Field of the Invention
The present invention relates to a level shifter, and more particularly, to a level shifter used in a Thin Film Transistor Liquid Crystal Display (TFT-LCD) driver.
2. Description of Related Art
A level shifter is a circuit that changes a first low-potential voltage level into a second high-potential voltage level. Typically, several hundred level shifters are included in a TFT-LCD driver. Thus, an increase in peak currents in the level shifters results in an increase in power consumption of the driver. Thus, to decrease the power consumption in the driver, the peak currents in the level shifters need to be reduced.
FIG. 1 is a circuit diagram of a conventional level shifter used in a TFT-LCD driver. FIG. 2 is a timing diagram illustrating the operation of the conventional level shifter shown in FIG. 1.
Referring to FIG. 1, the conventional level shifter includes. PMOS transistors MP1 through MP4, NMOS transistors MN1 and MN2, and inverters INV1 through INV3. In FIG. 1, VCC denotes a first voltage level and VDD denotes a second voltage level that has a higher electric potential than the first voltage level VCC. DATA denotes an input signal whose level changes between the first voltage level VCC and a ground voltage level VSS.
More specifically, when the input signal DATA is at the first voltage level VCC, the first PMOS transistor MP1 is turned off and the first NMOS transistor MN1 is turned on, thus lowering the level of a signal at a first node N1 to the ground level VSS. Also, the first inverter INV1 makes an inversion signal DATAB of the input signal DATA, DATAB having a logic low level, e.g., the ground level VSS, and as a result, the third PMOS transistor MP3 is turned on and the second NMOS transistor MN2 is turned off. The fourth PMOS transistor MP4 is turned on in response to the signal at the first node N1 having the ground voltage level VSS. The level of a signal at a second node N2 is increased to the second voltage level VDD. The second PMOS transistor MP2 is turned off in response to a signal at the second node N2. Therefore, an output signal OUT and a complementary output signal OUTB reach the second voltage level VDD and the ground level VSS, respectively.
When the input signal DATA is at the ground voltage level VSS, the first PMOS transistor MP1 is turned on and the first NMOS transistor MN1 is turned off. The inversion signal DATAB of the input signal DATA is at a logic high level, e.g., the first voltage level VCC, and the third PMOS transistor MP3 is turned off and the second NMOS transistor MN2 is turned on. The level of the signal at the second node N2 is lowered to the ground voltage level VSS and the second PMOS transistor MP2 is turned on. The level of the signal at first node N1 is raised to the level of the second voltage level VDD. Also, when the level of the signal at first node N1 changes, the fourth PMOS transistor MP4 is completely turned off. Accordingly, the levels of the output signal OUT and the complementary output signal OUTB reach the ground voltage level VSS and the second voltage level VDD, respectively.
Voltages at the nodes N1 and N2 of the second and fourth PMOS transistor MP2 and MP4, which are cross-coupled to each other, overlap at a point before they reach high and low levels, respectively. Thus, undesired overlap current paths are formed among the first and second PMOS transistors MP1 and MP2 and the first NMOS transistor MN1 and among the third and fourth PMOS transistors MP3 and MP4 and the second NMOS transistor MN2. Gates of a fifth PMOS transistor MP5 and a fifth NMOS transistor MN5, which are included in the second inverter INV2, are connected to the second node N2. Therefore, the fifth PMOS transistor MP5 and the fifth NMOS transistor MN5 are affected directly by the overlap current paths, increasing a total peak current.
Accordingly, it is important to minimize the amount of the total peak current generated by level shifters in a display device, such as the TFT-LCD.